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1 ? fn6299.1 isl9003a low noise ldo with low i q , high psrr isl9003a is a high performance single low noise, high psrr ldo that delivers a continuous 150ma of load current. it has a low standby current and is stable with 1 f of mlcc output capacitance with an esr of up to 200m . the isl9003a has a very high psrr of 90db and output noise is 20 v rms (typical). when coupled with a no load quiescent current of 31 a (typical), and 0.5 a shutdown current, the isl9003a is an ideal choice for portable wireless equipment. the isl9003a comes in many fixed voltage options with 1.8% output voltage accuracy over temperature, line and load. other output voltage options are available on request. pinouts isl9003a (5 ld sc-70) top view isl9003a (6 ld 1.6x1.6 tdfn ) top view features ? high performance ldo with 150ma continuous output ? excellent transient response to large current steps ? excellent load regulation: <0.1% voltage change across full range of load current ? very high psrr: >90db @ 1khz ? wide input voltage capability: 2.3v to 6.5v ? extremely low quiescent current: 31 a ? low dropout voltage: typically 200mv @ 150ma ? low output noise: typically 20 v rms @ 100 a (1.5v) ? stable with 1f to 4.7 f ceramic capacitors ? shutdown pin turns off ldo with 1 a (max) standby current ? soft-start limits input current surge during enable ? current limit and overheat protection ? 1.8% accuracy over all operating conditions ? 5 ld sc-70 package or 6 ld tdfn package ? -40c to +85c operating temperature range ? pb-free plus anneal available (rohs compliant) applications ? pdas, cell phones and smart phones ? portable instruments, mp3 players ? handheld devices including medical handhelds vin gnd en vo cbyp 1 2 3 5 4 nc 5 vo gnd cbyp vin en 1 2 3 6 4 5 data sheet december 21, 2006 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2006. all rights reserved. all other trademarks mentioned are the property of their respective owners.
2 fn6299.1 december 21, 2006 ordering information part number (note 2) part marking v o voltage (v) (note 1) temp. range (c) package tape and reel (pb-free) pkg. dwg. # isl9003aienz-t cbk 3.3 -40 to +85 5 ld sc-70 p5.049 isl9003aiemz-t cbj 3.0 -40 to +85 5 ld sc-70 p5.049 isl9003aiekz-t cce 2.85 -40 to +85 5 ld sc-70 p5.049 isl9003aiejz-t ccd 2.8 -40 to +85 5 ld sc-70 p5.049 isl9003aiehz-t ccc 2.75 -40 to +85 5 ld sc-70 p5.049 isl9003aiefz-t ccb 2.5 -40 to +85 5 ld sc-70 p5.049 isl9003aiecz-t cby 1.8 -40 to +85 5 ld sc-70 p5.049 isl9003aiebz-t cbw 1.5 -40 to +85 5 ld sc-70 p5.049 isl9003airubz-t l 1.5 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9003airucz-t g 1.8 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9003airufz-t f 2.5 -40 to +85 6 ld tdfn l6.1.6x1.6a ISL9003AIRUHZ-T h 2.75 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9003airujz-t j 2.8 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9003airukz-t k 2.85 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9003airumz-t m 3.0 -40 to +85 6 ld tdfn l6.1.6x1.6a isl9003airunz-t n 3.30 -40 to +85 6 ld tdfn l6.1.6x1.6a notes: 1. for other output voltages, contact intersil marketing. 2. intersil pb-free plus anneal products empl oy special pb-free material sets; molding compounds/die attach materials and 100% m atte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow tem peratures that meet or exceed the pb-free requirements of ipc/jedec j std-020. isl9003a
3 fn6299.1 december 21, 2006 absolute maximum rati ngs thermal information supply voltage (vin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to (vin+0.3v) recommended operating conditions ambient temperature range (t a ) . . . . . . . . . . . . . . .-40c to +85c supply voltage (vin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 to 6.5v thermal resistance ja (c/w) 5 ld sc-70 package (note 3) . . . . . . . . . . . . . . . . . 231 6 ld tdfn package (note 4) . . . . . . . . . . . . . . . . 125 junction temperature range . . . . . . . . . . . . . . . . .-40c to +125c operating temperature range . . . . . . . . . . . . . . . . .-40c to +85c storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 3. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 4. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. electrical specifications unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: t a = -40c to +85c; v in = (v o +0.5v) to 6.5v with a minimum v in of 2.3v; c in =1 f; c o = 1 f; c byp =0.01 f parameter symbol test conditions min typ max units dc characteristics supply voltage v in 2.3 6.5 v ground current i dd output enabled; i o = 0 a; v in < 4.2v 31 40 a output enabled; i o = 0 a; full voltage range 57 a shutdown current i dds 0.5 1.2 a uvlo threshold v uv+ 1.9 2.1 2.3 v v uv- 1.6 1.8 2.0 v regulation voltage accuracy initial accuracy at v in = v o +0.5v, i o = 10ma, t j = +25c -0.7 +0.7 % v in = v o +0.5v to 6.5v, i o = 10 a to150ma, t j = +25c -0.8 +0.8 % v in = v o +0.5v to 6.5v, i o = 10 a to 150ma, t j = -40c to +125c -1.8 +1.8 % maximum output current i max continuous 150 ma internal current limit i lim 175 265 355 ma drop-out voltage (note 6) v do1 i o = 150ma; v o < 2.5v 300 500 mv v do2 i o = 150ma; 2.5v v o 2.8v 250 400 mv v do3 i o = 150ma; 2.8v < v o 200 325 mv thermal shutdown temperature t sd+ 140 c t sd- 110 c ac characteristics ripple rejection (note 5) i o = 10ma, v in = 2.8v(min), v o = 1.8v, c byp = 0.1f @ 1khz 90 db @ 10khz 70 db @ 100khz 50 db output noise voltage (note 5) v o = 1.5v, t a = +25c, c byp = 0.1f bw = 10hz to 100khz, i o = 100 a20 v rms bw = 10hz to 100khz, i o = 10ma 30 v rms device start-up characteristics device enable time t en time from assertion of the en pin to when the output voltage reaches 95% of the vo(nom). 250 500 s ldo soft-start ramp rate t ssr slope of linear portion of ldo output voltage ramp during start-up 30 60 s/v isl9003a
4 fn6299.1 december 21, 2006 en pin characteristics input low voltage v il -0.3 0.4 v input high voltage v ih 1.4 v in +0.3 v input leakage current i il , i ih 0.1 a pin capacitance c pin informative 5 pf notes: 5. guaranteed by design and characterization 6. v o = 0.98 * v o (nom); valid for v o greater than 1.85v. electrical specifications unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: t a = -40c to +85c; v in = (v o +0.5v) to 6.5v with a minimum v in of 2.3v; c in =1 f; c o = 1 f; c byp =0.01 f (continued) parameter symbol test conditions min typ max units typical performance curves figure 1. output voltage vs input voltage (3.3v output) figure 2. output voltagechange (%) vs input voltage (3.3v output) figure 3. output voltage vs load current figure 4. output voltage vs temperature output voltage, v o (%) input voltage (v) -0.6 -0.2 0.2 0.6 -0.8 3.8 4.2 6.2 5.8 6.6 3.4 4.6 5.0 5.4 -0.4 0.0 0.4 0.8 v o = 3.3v +85 c -40 c +25 c i load = 0ma output voltage change (%) input voltage (v) v o = 3.3v i o = 0ma i o = 75ma i o = 150ma +25c 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 3.3 3.8 4.3 4.8 5.3 5.8 6.3 load current - i o (ma) output voltage change (%) +85c -40c +25c 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 25 50 75 100 125 150 175 v in = 3.8v v o = 3.3v 0.04 0.06 -0.06 -0.10 -25 0 25 85 -40 temperature ( c) output voltage (%) -0.02 0.00 0.02 0.08 0.10 -0.04 -0.08 55 v in = 3.8v v o = 3.3v i o = 0ma i o = 75ma i o = 150ma isl9003a
5 fn6299.1 december 21, 2006 figure 5. dropout voltage vs input voltage (3.3v output) figure 6. dropout voltage vs input voltage (2.8v output) figure 7. dropout vo ltage vs load current figure 8. dropout voltage vs load current figure 9. ground current vs input voltage figure 10. ground current vs load typical performance curves (continued) output voltage, v o (v) input voltage (v) 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.6 3.1 3.6 4.1 4.6 5.1 5.6 6.1 6.6 i o = 150ma i o = 0ma i o = 75ma v o = 3.3v +25c input voltage (v) output voltage, v o (v) v o = 2.8v 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 i o = 150ma i o = 0ma i o = 75ma +25c output load (ma) v o = 2.8v v o = 3.3v drop out voltage, v do (mv) 250 200 150 100 50 0 0 25 50 75 100 125 150 175 100 125 150 175 75 25 0 25 50 75 100 125 150 175 0 output load (ma) drop out voltage, v do (mv) v o = 3.3v +85 c +25 c -40 c 225 50 200 10 20 30 40 60 0 2.5 3.5 5.0 input voltage (v) ground current (a) 50 1.5 2.0 3.0 4.0 4.5 -40 c +85 c 6.0 5.5 6.5 i o = 0a v o = 3.3v +25 c 100 20 0 25 50 75 100 125 0 load current (ma) ground current (a) 175 150 v o = 3.3v v in = 3.8v 40 60 80 120 140 +85 c -40 c +25 c isl9003a
6 fn6299.1 december 21, 2006 figure 11. ground current vs temperat ure figure 12. turn on/turn off response figure 13. line transient response, 3.3v output figure 14. line transient response, 2.8v output figure 15. load transient response figure 16. psrr vs frequency typical performance curves (continued) 40 20 -20 0 20 60 -40 temperature ( c) ground current (a) 60 70 80 50 30 -30 -10 10 40 30 50 70 v in = 3.8v v o = 3.3v 90 100 80 90 i l = 150ma i l = 75ma i l = 0ma 1 3 0 2 0 100 200 300 400 500 600 700 800 0 time (s) vo(v) ven (v) 5 v o = 3.3v v in = 5.0v i l = 150ma c l = 1f 900 1000 400 s/div v o = 3.3v i load = 150ma 3.6v 4.3v 10mv/div c load = 1 f c byp = 0.01 f 400 s/div v o = 2.8v i load = 150ma 3.5v 4.2v 10mv/div c load = 1 f c byp = 0.01 f 1.0 ms/div vo (10mv/div) i load 100ma 100 a v in = 3.8v v o = 3.3v 0.1k 1k 10k 100k 1m frequency (hz) 110 10 20 30 40 50 60 70 80 90 100 psrr (db) v in = 3.9v v o = 1.8v c byp = 0.1 f c load = 1 f 50ma 10ma isl9003a
7 fn6299.1 december 21, 2006 pin description typical application figure 17. spectral noise density vs frequency 5 ld sc-70 pin # 6 ld tdfn pin # pin name description 1 6 vin supply voltage/ldo input. connect a 1 f capacitor to gnd. 2 2 gnd gnd is the connection to system ground. connect to pcb ground plane. 3 4 en output enable. when this signal goes high, the ldo is turned on. 4 3 cbyp reference bypass capacitor pin. optionally connec t capacitor of value 0.01f to 1f between this pin and gnd to tune in the desired noise and psrr performance. 5 1 vo ldo output. connect a 1f capacitor of value to gnd. - 5 nc no connect. typical performance curves (continued) spectral noise density ( v/ hz ) 2.000 1.000 0.100 0.010 0.001 10 100 1k 10k 100k 1m frequency (hz) v in = 3.9v v o = 1.8v c byp = 0.1 f c in = 1 f c load = 1 f 100 a 10ma c1, c2: 1f x5r ceramic capacitor isl9003a (sc-70) vin gnd vo cbyp 5 4 1 2 vin (2.3-5v) vout c1 c2 en 3 enable off on c3 c3: 0.1f x5r ceramic capacitor c1, c2: 1f x5r ceramic capacitor isl9003a (tdfn) vo gnd vin en 5 4 1 2 vout c1 c2 cbyp 3 enable off on c3 c3: 0.1f x5r ceramic capacitor nc vin (2.3-5v) 6 isl9003a
8 fn6299.1 december 21, 2006 block diagram functional description the isl9003a contains all circuitry required to implement a high performance ldo. high performance is achieved through a circuit that deliver s fast transient response to varying load conditions. in a quiescent condition, the isl9003a adjusts its biasing to achieve the lowest standby current consumption. the device also integrates cu rrent limit protection, smart thermal shutdown protection, and soft-start. smart thermal shutdown protects the device aga inst overheating. soft-start minimizes start-up input current surges without causing excessive device turn-on time. power control the isl9003a has an enable pin, en, to control power to the ldo output. when en is low, the device is in shutdown mode. in this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.3 a. when the en pin goes high, the device first polls the output of the uvlo detector to ensure that vin voltage is at least 2.1v (typical). once verified, the device initiates a start-up sequence. during the start-up sequence, trim settings are first read and latched. then, sequentially, the bandgap, reference voltage and current generation circuitry turn on. once the references are stable, the ldo powers up. during operation, whenever the vin voltage drops below about 1.84v, the isl9003a im mediately disables the ldo output. when vin rises back above 2.1v (assuming the en pin is high), the device re-initiates its start-up sequence and ldo operation resumes automatically. reference generation the reference generation circuitry includes a trimmed bandgap, a trimmed voltage reference divider, a trimmed current reference generator, and an rc noise filter. the filter includes the external capacitor connected to the cbyp pin. a 0.01 f capacitor connected cbyp implements a 100hz lowpass filter, and is recommended for most high performance applications. for th e lowest noise application, a 0.1 f or greater cbyp capacitor sh ould be used. this filters the reference noise to below the 10hz ? 1khz frequency band, which is crucial in many noise-sensitive applications. the bandgap generates a zero temperature coefficient (tc) voltage for the regulator reference and other voltage references required for current generation and over- temperature detection. a current generator provides references required for adaptive biasing as well as references for ldo output current limit and thermal shutdown determination. ldo regulation and programmable output divider the ldo regulator is implemented with a high-gain operational amplifier driving a pmos pass transistor. the design of the isl9003a provides a regulator that has low quiescent current, fast transient response, and overall stability across all operating and load current conditions. ldo stability is guaranteed for a 1 f to 4.7 f output capacitor that has a tolerance better than 20% and esr less than 200m . the design is performance-optimized for a 1 f capacitor. unless limited by the application, use of an output capacitor value above 4.7 f is not recommended as ldo performance improvement is minimal. vo gnd bandgap and temperature sensor uvlo vin sd control logic voltage and reference generator cbyp 1.0v 0.94v 0.9v gnd short circuit, thermal protection, soft-start + - isl9003a
9 fn6299.1 december 21, 2006 soft-start circuitry integrated into each ldo limits the initial ramp-up rate to about 30 s/v to minimize current surge. the isl9003a provides short-circuit protection by limiting the output current to about 265ma (typ). the ldo uses an independently trimmed 1v reference as its input. an internal resistor divider drops the ldo output voltage down to 1v. this is compared to the 1v reference for regulation. the resistor division ratio is programmed in the factory. overheat detection the bandgap outputs a proportional-to-temperature current that is indicative of the temp erature of the silicon. this current is compared with refer ences to determine if the device is in danger of damage due to overheating. when the die temperature reaches about +140c, the ldo momentarily shuts down until the die cools sufficiently. in the overheat condition, if the ld o sources more than 50ma it will be shut off. once the die temperature falls back below about +110c, the disabled ldo is re-enabled and soft-start automatically takes place. isl9003a
10 fn6299.1 december 21, 2006 ultra thin dual flat no-l ead plastic package (utdfn) b d a e 0.15 c 2x pin 1 top view 0.15 c 2x reference detail a 0.10 c 0.08 c 6x a3 c seating plane l e 46 31 bottom view side view 0.10 cab b6x detail a 0.127 +0.058 a1 a1 a 0.1270.008 64 13 m co.2 1.00 ref d2 dap size 1.30 x 0.76 e2 -0.008 terminal thickness 0.30 1.00 0.45 0.50 0.25 1.25 2.00 1.00 land pattern 6 l6.1.6x1.6a 6 lead ultra thin dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.45 0.50 0.55 - a1 - - 0.05 - a3 0.127 ref - b 0.15 0.20 0.25 - d 1.55 1.60 1.65 4 d2 0.40 0.45 0.50 - e 1.55 1.60 1.65 4 e2 0.95 1.00 1.05 - e 0.50 bsc - l 0.25 0.30 0.35 - rev. 1 6/06 notes: 1. dimensions are in mm. angles in degrees. 2. coplanarity applies to the exposed pad as well as the terminals. coplanarity shall not exceed 0.08mm. 3. warpage shall not exceed 0.10mm. 4. package length/package width are considered as special characteristics. 5. jedec reference mo-229. 6. for additional information, to assist with the pcb land pattern design effort, see intersil technical brief tb389. isl9003a
11 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6299.1 december 21, 2006 isl9003a small outline transistor plastic packages (sc70-5) d e 1 e e1 c l c c l e b c l a2 a a1 c l 0.20 (0.008) m 0.10 (0.004) c c -c- seating plane 4 5 123 view c view c l r1 r 4x 1 4x 1 gauge plane l1 seating l2 c plane c base metal with c1 b1 plating b p5.049 5 lead small outline transistor plastic package symbol inches millimeters notes min max min max a 0.031 0.043 0.80 1.10 - a1 0.000 0.004 0.00 0.10 - a2 0.031 0.039 0.80 1.00 - b 0.006 0.012 0.15 0.30 - b1 0.006 0.010 0.15 0.25 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.009 0.08 0.20 6 d 0.073 0.085 1.85 2.15 3 e 0.071 0.094 1.80 2.40 - e1 0.045 0.053 1.15 1.35 3 e 0.0256 ref 0.65 ref - e1 0.0512 ref 1.30 ref - l 0.010 0.018 0.26 0.46 4 l1 0.017 ref. 0.420 ref. - l2 0.006 bsc 0.15 bsc 0 o 8 o 0 o 8 o - n5 55 r 0.004 - 0.10 - r1 0.004 0.010 0.15 0.25 rev. 2 9/03 notes: 1. dimensioning and tolerances per asme y14.5m-1994. 2. package conforms to eiaj sc70 and jedec mo-203aa. 3. dimensions d and e1 are exclusiv e of mold flash, protrusions, or gate burrs. 4. footlength l measured at reference to gauge plane. 5. ?n? is the number of terminal positions. 6. these dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. controlling dimension: millime ter. converted inch dimen- sions are for reference only.

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